In a computer system, various buses are provided for interconnecting a host processor(s) and other devices and transferring data among them. As an example, PCIe has been developed for replacing the older Peripheral Component Interconnect (PCI) and PCI-X standards. PCIe is used in consumer, server, and industrial applications as a motherboard-level interconnect to link motherboard-mounted peripherals and as an expansion card interface for add-in boards.
A difference between PCIe and earlier PCI or PCI-X buses is a topology based on point-to-point serial links, rather than a shared parallel bus architecture. PCIe can be thought of as a high-speed serial replacement of the older parallel PCI and PCI-X bus. At the software-level, PCIe preserves compatibility with PCI so that a PCIe device can be configured and used in legacy applications and operating systems which have no direct knowledge of the new features of PCIe.
In PCIe 1.0 or 1.1, each lane carries 250 MB/s. PCIe 2.0, released in late 2007, adds a second generation signaling mode, doubling the rate to 500 MB/s. PCIe 3.0, currently in development, will add a third generation signaling mode at 1 GB/s.
PCIe 2.0 and 3.0 also maintain compatibility with the earlier generation of PCIe (i.e., PCIe 1.x). Since PCIe 1.x compatible devices are still being used in the market, PCIe 2.0 or 3.0 compatible devices may need to be connected with PCIe 1.x compatible devices. A PCIe 2.0 or 3.0 device may need to switch clock speeds as required by one of the ports and have the clock speed updated, glitch-free, within a certain period of time without interrupting data transfers on any of the other ports.